1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a MOS transistors where the gate is etched to reduce the channel length.
2) Description of the Prior Art
As semiconductor devices are scaled down, there is a need to more accurately control the gate width and channel width. There is a need to find a process that allows channel regions and gate widths to more accurately controlled. There is also a need to find a process that allows channel regions and gate widths to more reduced below the lithographic limits.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,334,545(Caviglia) shows method for forming a gate and etching the poly bottom gate material.
U.S. Pat. No. 4,528,066(Merkling, Jr., et al.) shows process to eliminate undercutting under a gate.
U.S. Pat. No. 6,037,630(Igarashi et al.) shows a gate process.
U.S. Pat. No. 5,786,253(Hsu) shows a ROM cell with conductive lines.